
// Library name: VLSI_Project
// Cell name: 2_to_1_Mux
// View name: schematic
subckt VLSI_Project_2_to_1_Mux_schematic Bulk out s sb x0 x1
    M1 (out s x1 Bulk) NMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 \
        ps=300n pd=300n ld=105n ls=105n m=1
    M0 (out sb x0 Bulk) NMOS_VTL w=90n l=50n as=9.45e-15 ad=9.45e-15 \
        ps=300n pd=300n ld=105n ls=105n m=1
ends VLSI_Project_2_to_1_Mux_schematic
// End of subcircuit definition.

// Library name: VLSI_Project
// Cell name: 16_to_1_Mux
// View name: schematic
subckt VLSI_Project_16_to_1_Mux_schematic Bulk out s0 s1 s2 s3 sb0 sb1 sb2 \
        sb3 x0 x1 x10 x11 x12 x13 x14 x15 x2 x3 x4 x5 x6 x7 x8 x9
    I14 (Bulk out s3 sb3 net30 net35) VLSI_Project_2_to_1_Mux_schematic
    I13 (Bulk net35 s2 sb2 net53 net37) VLSI_Project_2_to_1_Mux_schematic
    I12 (Bulk net30 s2 sb2 net42 net59) VLSI_Project_2_to_1_Mux_schematic
    I11 (Bulk net37 s1 sb1 net48 net49) VLSI_Project_2_to_1_Mux_schematic
    I10 (Bulk net53 s1 sb1 net54 net83) VLSI_Project_2_to_1_Mux_schematic
    I9 (Bulk net59 s1 sb1 net101 net95) VLSI_Project_2_to_1_Mux_schematic
    I8 (Bulk net42 s1 sb1 net66 net67) VLSI_Project_2_to_1_Mux_schematic
    I7 (Bulk net49 s0 sb0 x14 x15) VLSI_Project_2_to_1_Mux_schematic
    I6 (Bulk net48 s0 sb0 x12 x13) VLSI_Project_2_to_1_Mux_schematic
    I5 (Bulk net83 s0 sb0 x10 x11) VLSI_Project_2_to_1_Mux_schematic
    I4 (Bulk net54 s0 sb0 x8 x9) VLSI_Project_2_to_1_Mux_schematic
    I3 (Bulk net95 s0 sb0 x6 x7) VLSI_Project_2_to_1_Mux_schematic
    I2 (Bulk net101 s0 sb0 x4 x5) VLSI_Project_2_to_1_Mux_schematic
    I1 (Bulk net67 s0 sb0 x2 x3) VLSI_Project_2_to_1_Mux_schematic
    I0 (Bulk net66 s0 sb0 x0 x1) VLSI_Project_2_to_1_Mux_schematic
ends VLSI_Project_16_to_1_Mux_schematic
// End of subcircuit definition.

// Library name: VLSI_Project
// Cell name: Param_Inverter
// View name: schematic
subckt Param_Inverter VDD VSS in out
parameters nw=90n nl=50n pw=180n pl=50n
    M5 (out in VSS VSS) NMOS_VTL w=nw l=nl as=9.45e-15 ad=9.45e-15 ps=300n \
        pd=300n ld=105n ls=105n m=1
    M4 (out in VDD VDD) PMOS_VTL w=pw l=pl as=1.89e-14 ad=1.89e-14 \
        ps=390.0n pd=390.0n ld=105n ls=105n m=1
ends Param_Inverter
// End of subcircuit definition.

// Library name: VLSI_Project
// Cell name: TB_16_to_1_Mux_Bus
// View name: schematic
I0 (0 MuxOut Vin0Buf Vin1Buf Vin2Buf Vin3Buf Vin0BufB Vin1BufB Vin2BufB \
        Vin3BufB Vx\<0\> Vx\<1\> Vx\<10\> Vx\<11\> Vx\<12\> Vx\<13\> \
        Vx\<14\> Vx\<15\> Vx\<2\> Vx\<3\> Vx\<4\> Vx\<5\> Vx\<6\> Vx\<7\> \
        Vx\<8\> Vx\<9\>) VLSI_Project_16_to_1_Mux_schematic
C0 (InvOut 0) capacitor c=pOutCap
V6 (net074 0) vsource dc=pVDDL type=dc
VHSUPPLY (VDDH 0) vsource dc=pVDDH type=dc
V1 (net073 0) vsource dc=pVDDH type=dc
I53 (VDDH 0 Vin0BufB Vin0Buf) Param_Inverter nw=90n nl=50n pw=180n pl=50n
I59 (VDDH 0 Vin3 Vin3BufB) Param_Inverter nw=90n nl=50n pw=180n pl=50n
I58 (VDDH 0 Vin3BufB Vin3Buf) Param_Inverter nw=90n nl=50n pw=180n pl=50n
I57 (VDDH 0 Vin2BufB Vin2Buf) Param_Inverter nw=90n nl=50n pw=180n pl=50n
I56 (VDDH 0 Vin2 Vin2BufB) Param_Inverter nw=90n nl=50n pw=180n pl=50n
I55 (VDDH 0 Vin1 Vin1BufB) Param_Inverter nw=90n nl=50n pw=180n pl=50n
I54 (VDDH 0 Vin1BufB Vin1Buf) Param_Inverter nw=90n nl=50n pw=180n pl=50n
I71 (net073 0 In1 Vin1) Param_Inverter nw=90n nl=50n pw=180n pl=50n
I70 (net073 0 In0 Vin0) Param_Inverter nw=90n nl=50n pw=180n pl=50n
I72 (net073 0 In2 Vin2) Param_Inverter nw=90n nl=50n pw=180n pl=50n
I73 (net073 0 In3 Vin3) Param_Inverter nw=90n nl=50n pw=180n pl=50n
INV\<0\> (VDDL 0 SRAM\<0\> Vx\<0\>) Param_Inverter nw=90n nl=50n pw=180n \
        pl=50n
INV\<1\> (VDDL 0 SRAM\<1\> Vx\<1\>) Param_Inverter nw=90n nl=50n pw=180n \
        pl=50n
INV\<2\> (VDDL 0 SRAM\<2\> Vx\<2\>) Param_Inverter nw=90n nl=50n pw=180n \
        pl=50n
INV\<3\> (VDDL 0 SRAM\<3\> Vx\<3\>) Param_Inverter nw=90n nl=50n pw=180n \
        pl=50n
INV\<4\> (VDDL 0 SRAM\<4\> Vx\<4\>) Param_Inverter nw=90n nl=50n pw=180n \
        pl=50n
INV\<5\> (VDDL 0 SRAM\<5\> Vx\<5\>) Param_Inverter nw=90n nl=50n pw=180n \
        pl=50n
INV\<6\> (VDDL 0 SRAM\<6\> Vx\<6\>) Param_Inverter nw=90n nl=50n pw=180n \
        pl=50n
INV\<7\> (VDDL 0 SRAM\<7\> Vx\<7\>) Param_Inverter nw=90n nl=50n pw=180n \
        pl=50n
INV\<8\> (VDDL 0 SRAM\<8\> Vx\<8\>) Param_Inverter nw=90n nl=50n pw=180n \
        pl=50n
INV\<9\> (VDDL 0 SRAM\<9\> Vx\<9\>) Param_Inverter nw=90n nl=50n pw=180n \
        pl=50n
INV\<10\> (VDDL 0 SRAM\<10\> Vx\<10\>) Param_Inverter nw=90n nl=50n \
        pw=180n pl=50n
INV\<11\> (VDDL 0 SRAM\<11\> Vx\<11\>) Param_Inverter nw=90n nl=50n \
        pw=180n pl=50n
INV\<12\> (VDDL 0 SRAM\<12\> Vx\<12\>) Param_Inverter nw=90n nl=50n \
        pw=180n pl=50n
INV\<13\> (VDDL 0 SRAM\<13\> Vx\<13\>) Param_Inverter nw=90n nl=50n \
        pw=180n pl=50n
INV\<14\> (VDDL 0 SRAM\<14\> Vx\<14\>) Param_Inverter nw=90n nl=50n \
        pw=180n pl=50n
INV\<15\> (VDDL 0 SRAM\<15\> Vx\<15\>) Param_Inverter nw=90n nl=50n \
        pw=180n pl=50n
I77 (net074 0 MuxOut InvOut) Param_Inverter nw=90n nl=50n pw=180n pl=50n
I52 (VDDH 0 Vin0 Vin0BufB) Param_Inverter nw=90n nl=50n pw=180n pl=50n
VLSUPPLY (VDDL 0) vsource dc=pVDDL type=dc
